minimal hypervisor for aarch64 (WIP)
Find a file
2025-10-29 01:39:05 +00:00
include priority scheduling for mixed workloads 2025-10-29 01:39:05 +00:00
src priority scheduling for mixed workloads 2025-10-29 01:39:05 +00:00
.gitignore replace raw s3_* sysregs w HCR_EL2/CPTR_EL2/SCTLR_EL1 macros 2025-10-28 14:33:30 +00:00
guest.S initial commit 2025-10-28 13:54:32 +00:00
linker.ld update memory layout/build + enable tracing and fix trace event handling 2025-10-28 14:41:44 +00:00
Makefile worked on per guest stage2 page tables and memory isolation + guest bounds validation and virtualised uart per guest 2025-10-28 14:55:53 +00:00
README.txt updated README.txt for my own sanity 2025-10-28 14:04:18 +00:00

┌─────────────────────────────────────────────────────────────────────────────┐
│  OVERVIEW                                                                   │
└─────────────────────────────────────────────────────────────────────────────┘

lyra is a current WIP arm64 type1 hypervisor executing at el2 privilege level.
it implements full hardware virtualisation w stage2 page
tables, vcpu context switching and exception vector routing

arm virtualization extensions provide hardware assisted capabilities:
~ stage2 address translation via vtcr_el2 and vttbr_el2
~ cpu state management w full register context
~ exception handling and trap and emulate semantics
~ mmu virtualisation w nested page table walks
~ device emulation (uart virtualisation)

┌─────────────────────────────────────────────────────────────────────────────┐
│  ARCHITECTURAL OVERVIEW                                                     │
└─────────────────────────────────────────────────────────────────────────────┘

the hypervisor implements ur typical vmm architecture:

HOST (EL2)                    GUEST (EL1)
┌─────────────┐              ┌─────────────┐
│   lyra      │              │   guest     │
│ hypervisor  │◄────────────►│   kernel    │
│             │              │             │
└─────────────┘              └─────────────┘
       │                            │
       ▼                            ▼
┌─────────────┐              ┌─────────────┐
│ stage1 mmu  │              │ stage1 mmu  │
│ (host PTs)  │              │ (guest PTs) │
└─────────────┘              └─────────────┘
       │                            │
       ▼                            ▼
┌─────────────────────────────────────────┐
│         stage2 mmu                      │
│    (address translation)                │
└─────────────────────────────────────────┘
       │
       ▼
┌─────────────┐
│  hardware   │
│  memory     │
└─────────────┘


┌─────────────────────────────────────────────────────────────────────────────┐
│  MEMORY LAYOUT                                                              │
└─────────────────────────────────────────────────────────────────────────────┘

physical memory map:
┌─────────────────────────────────────────────────────────────────────────────┐
│ 0x40000000 - 0x43ffffff │ host hypervisor code/data (64mb)                  │
│ 0x44000000 - 0x47ffffff │ guest vm memory space (64mb)                      │
│ 0x09000000 - 0x09000fff │ uart mmio region (4kb)                            │
└─────────────────────────────────────────────────────────────────────────────┘

virtual memory layout (guest):
┌─────────────────────────────────────────────────────────────────────────────┐
│ 0x40000000 - 0x43ffffff │ guest physical memory                             │
│ 0x09000000 - 0x09000fff │ virtualized uart device                           │
└─────────────────────────────────────────────────────────────────────────────┘